newhaven display international, llc nhd-0 440az users guide nhd-0440a z-fl-gbw lcm (liquid crystal display character module) rohs compliant features z display format: 4 lines x 40 characters z ( a ) C display series/model z ( z ) C factory line z ( f ) C polarizer = trans flective ( + ) light method z ( l ) C backlight = led ( yellow-green) z ( g ) C lcd type = s tn- gray z ( b ) C view direction = 6:00 z (w) C operating temp. = wide ( -2 0~+ 7 0c) lcd driver ic: s plc780d for product support, contact newhaven display international, llc 2 511 technology drive , #101 elgin, il 601 24 tel: (847) 8 44-8795 fax: (847) 8 44-8796 october 16, 200 7
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nhd-0440az interface pin description pin no. symbol external connection function 1~4 db7~db4 mpu four high order bi-directi onal three-state data bus lines. used for data transfer between the mpu 5~8 db3~db0 mpu four low order bi-directional three-state data bus lines. used for data transfer between the mpu and the lcm. these four are not used during 4-bit operation. 9 e1 mpu operation (data read/write) enable signal 10 r/w mpu read/write select signal 11 rs mpu register select signal 12 v 0 contrast adjust 13 v ss signal ground for lcm (gnd) 14 v dd power supply power supply for logic (+5v) for lcm 15 e2 mpu enable signal (no pull-up resistor) 16 nc 17 led+ power supply for led backlight (+5v) 18 led- power supply power supply for led backlight (0v) contrast adjust a ? for single source b) for double source for module with normal temperature range fluid for module with extended temperature range fluid or wide viewing cone fluid v dd~ v 0 : lcd driving voltage vr: 1k~2k electrical characteristics backlight circuit di agram (light 48 x 2) led ratings (yellow/green) (uak = 4.2v, ta =25 ) item symbol min typ. max unit forward voltage vak 3.6 4.2 4.3 v forward current if - 480 500 ma power p 2016 mw peak wave length p570 nm luminance lv 80 cd/m2 v: a 2/9 01/31/2007
nhd-0440az stn type display module (ta=25 , vdd=5.0v) item symbol condition min. typ. max. unit ? -60 - 35 viewing angle ? c r 12 -40 -40 deg contrast ratio c r -6-- response time (rise) t r - - 150 250 response time (fall) t r - - 150 250 ms electrical characteristics dc characteristics parameter symbol conditions min. typ. max. unit supply voltage for lcd v dd -v 0 ta =25 - 5.0 - input voltage v dd 2.7 - 5.5 v supply current i dd ta=25 , v dd =5.0v - 3.5 4.0 ma input leakage current i lkg - - 5.0 ua ?h? level input voltage v ih 2.2 - v dd ?l? level input voltage v il twice initial value or less 0 - 0.6 ?h? level output voltage v oh loh=-0.25ma 2.4 - - ?l? level output voltage v ol loh=1.6ma - - 0.4 backlight supply voltage v f - - 5.0 v backlight supply current i f v f =5.0v -480 - ma read cycle (ta=25 , vdd=5.0v) parameter symbol test pin min. typ. max. unit enable cycle time t c 500 - - enable pulse width t w 300 - - enable rise/fall time t r, t f e --25 rs; r/w setup time t su 100 - - rs; r/w address hold time t h rs; r/w rs; r/w 10 - - read data output delay t d 60 - 90 read data hold time t dh db0~db7 20 - - ns write cycle (ta=25 , vdd=5.0v) parameter symbol test pin min. typ. max. unit enable cycle time t c 500 - - enable pulse width t w 300 - - enable rise/fall time t r, t f e --25 rs; r/w setup time t su1 100 - - rs; r/w address hold time t h1 rs; r/w rs; r/w 10 - - read data output delay t su2 60 - - read data hold time t h2 db0~db7 10 - - ns v: a 3/9 01/31/2007
nhd-0440az write mode timing diagram read mode timing diagram block diagram v: a 4/9 01/31/2007
nhd-0440az instruction description outline to overcome the speed difference betwe en the internal clock of ks0066u and the mpu clock , ks0066u performs internal operations by storing co ntrol in formations to ir or dr. the internal operation is determined according to the signal from mpu, composed of read/write and data bus (refer to table7). instructions can be divid ed largely in to four groups: 1) ks0066u function set instructions (set display methods, set data length, etc.) 2) address set instructions to internal ram 3) data transfer instructions with internal ram 4) others the address of the internal ram is automatically increased or decreased by 1. note: during internal operation, busy flag (db7) is read ?high?. busy flag check must be preceded by the next instruction. when an mpu program with checking th e busy flag (db7) is made, it must be necessary 1/2 fuss for executing the next instruction by the falling edge of the ?e? signal after the busy flag (db7) goes to ?low?. contents 1) clear display rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0000000001 clear all the display data by writing ?20h? (space code) to all ddram address, and set ddram address to ?00h? into ac (address counter). return cursor to the original status, namely , brings the cursor to the left ed ge on the fist line of the display. make the entry mode increment (i/d=?high?). 2) return home rs r/w db7 db6 db5 db4 db3 db2 db1 db0 000000001- return home is cursor return home instruction. set ddram address to ?00h? int o the address counter. return cursor to its original site and return dis play to its origina l status, if shifted. contents of ddram does not change. 3) entry mode set rs r/w db7 db6 db5 db4 db3 db2 db1 db0 00000000i/d sh set the moving direction of cursor and display. i/d: increment / decrement of ddram address (cursor or blink) when i/d=?high?, cursor/blink moves to right and ddram address is increased by 1. when i/d=?low?, cursor/blink moves to left and ddram address is increased by 1. *cgram operates the same way as ddram, when reading from or writing to cgram. (i/d=?high?. shift left, i/d=?low?. shift right). v: a 5/9 01/31/2007
nhd-0440az 4) display on/off control rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0000001d cb control display/cursor/blink on/off 1 bit register. d: display on/off control bit when d=?high?, entire display is turned on. when d=?low?, display is turned off, but display data remains in ddram. c: cursor on/off control bit when d=?high?, cursor is turned on. when d=?low?, cursor is disappeared in current display, but i/d register preserves its data. b: cursor blink on/off control bit when b=?high?, cursor blink is on, which performs alternately between all the ?hi gh? data and display characters at the cursor position. when b=?low?, blink is off. 5) cursor or display shift rs r/w db7 db6 db5 db4 db3 db2 db1 db0 000001s/cr/l- - shifting of right/left cursor posi tion or display witho ut writing or reading of display data. this instruction is used to correct or search display data. (refer to table 6) during 2-line mode display, cursor moves to the 2 nd line after the 40 th digit of the 1 st line. when display data is shifted repeatedly , each line is s hifted individually. when display shift is performed, the cont ents of the address counter are not changed. shift patterns according to s/c and r/l bits s/c r/l operation 0 0 shift cursor to the left, ac is decreased by 1 0 1 shift cursor to the righ t, ac is increased by 1 1 0 shift all the display to the left, cursor moves according to the display 1 1 shift all the display to the right, cursor moves according to the display 6) function set rs r/w db7 db6 db5 db4 db3 db2 db1 db0 00001dl n f- - dl: interface data length control bit when dl=?high?, it mans 8-bit bus mode with mpu. when dl=?low?, it mans 4-bit bus mode with mpu. hence, dl is a signal to select 8-bit or 4-bit bus mode. when 4-but bus mode, it needs to transfer 4-bit data twice. n: display line number control bit when n=?low?, 1-line display mode is set. when n=?high?, 2-line display mode is set. v: a 6/9 01/31/2007
nhd-0440az f: display line number control bit when f=?low?, 5x8 dots form at display mode is set. when f=?high?, 5x11 dots format display mode. 7) set cgram address rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 ac5 ac4 ac3 ac2 ac1 ac0 set cgram address to ac. the instruction makes cgram data available from mpu. 8) set ddram address rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 ac6 ac5 ac4 ac3 ac2 ac1 ac0 set ddram address to ac. this instruction makes ddram data available form mpu. when 1-line display mode (n=low), ddram address is form ?00h? to ?4fh?. in 2-line display mode (n=high), ddram address in the 1 st line form ?00h? to ?27h?, and ddram address in the 2 nd line is from ?40h? to ?67h?. 9) read busy flag & address rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 1 bf ac6 ac5 ac4 ac3 ac2 ac1 ac0 this instruction shows whether ks0066u is in internal operation or not. if the resultant bf is ?h igh?, internal operation is in progress and should wait bf is to be low, which by then if the nest instruction can be performed. in this instruction you can also read the value of the address counter. 10) write data to ram rs r/w db7 db6 db5 db4 db3 db2 db1 db0 1 0 d7 d6 d5 d4 d3 d2 d1 d0 write binary 8-bit data to ddram/cgram. the selection of ram from ddram, and cgram, is set by the previous address set instruction (ddram address set, cgram address set). ram set instruction can also determine the ac direction to ram. after write operation. the address is automatically increased/decreased by 1, according to the entry mode. 11) read data from ram rs r/w db7 db6 db5 db4 db3 db2 db1 db0 1 1 d7 d6 d5 d4 d3 d2 d1 d0 read binary 8-bit data from ddram/cgram. the selection of ram is set by the previ ous address set instruction. if the ad dress set instruction of ram is not performed before this instruction, the data that has been read first is invalid, as the direction of ac is not yet determined. if ram data is read several times without ram address instructions set before, read operation, the correct ram data can be obtained from the second. but th e first data would be incorrec t, as there is no time margin to transfer ram data. in case of ddram read operation, cursor shift instruction plays the same role as ddram address set instruction, it also transfers ram data to output data register. after read operation, address counter is automatically increased/de creased by 1 according to the entry mode. v: a 7/9 01/31/2007
nhd-0440az after cgram read operation, display shift may not be executed correctly. note: in case of ram write operation, ac is increased/decreased by 1 as in read operation. at this time, ac indicates next address position, but only the previous data can be read by the read instruction. instruction table instruction code instruction rs r/ w db7 db6 db5 db4 db3 db2 db1 db0 description execution time (fosc= 270 khz clear display 0000000001 write ?20h? to ddra and set ddram address to ?00h? from ac 1.53ms return home 000000001- set ddram address to ?00h? from ac and return cursor to its original position if shifted. the contents of ddram are not changed. 1.53ms entry mode set 00000001i/d sh assign cursor moving direction and blinking of entire display 39us display on/ off control 0000001d c b set display (d), cursor (c), and blinking of cursor (b) on/off control bit. cursor or display shift 0 0 0 0 0 1 s/c r/l - - set cursor moving and display shift control bit, and the direction, without changing of ddram data. 39us function set 00001dl n f- - set interface data length (dl: 8- bit/4-bit), numbers of display line (n: =2-line/1-line) and, display font type (f: 5x11/5x8) 39us set cgram address 0 0 0 1 ac5 ac4 ac3 ac2 ac1 ac0 set cgram address in address counter. 39us set ddram address 0 0 1 ac6 ac5 ac4 ac3 ac2 ac1 ac0 set ddram address in address counter. 39us read busy flag and address 0 1 bf ac6 ac5 ac4 ac3 ac2 ac1 ac0 whether during internal operation or not can be known by reading bf. the contents of address counter can also be read. 0us write data to address 1 0 d7 d6 d5 d4 d3 d2 d1 d0 write data into internal ram (ddram/cgram). 43us read data from ram 1 1 d7 d6 d5 d4 d3 d2 d1 d0 read data from internal ram (ddram/cgram). 43us note: when an mpu program with checking the busy flag (db7) is made, it must be necessary 1/2fosc is necessary for executing the next instruction by the falling edge of the ?e? signal after the busy flag (db7) goes to ?low?. ddram address: display position 1 2 3 4 5 - - - - - - - - - - 36 37 38 39 40 00 01 02 03 04 - - - - - - - - - - 23 24 25 26 27 40 40 41 42 43 - - - - - - - - - - 63 64 65 66 67 00 01 02 03 04 - - - - - - - - - - 23 24 25 26 27 40 40 41 42 43 - - - - - - - - - - 63 64 65 66 67 ddram address v: a 8/9 01/31/2007
nhd-0440az standard character pattern v: a 9/9 01/31/2007
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